Yuchen Huang

Yuchen’s primary focus is on teaching and she directs the ECE MS graduate track in Digital IC Design. Prior to joining the ECE department, she was at Intel Corporation for 21 years in Hillsboro, Oregon, where she was a senior staff engineer, involved in key product development and industry adoption of technologies, standards, specifications and methodologies. She was the chairperson of cross-functional Joint Engineering Teams at Intel and industry consortium JEDEC DDR2 Memory Power Thermal Task Group, addressing system level memory power, thermal, and performance challenges. She has extensive experience in platform design, power management architecture and led the development of Intel’s Converged Platform Power Thermal Throttling Specification that maximizes re-usability across CPU generations and computing segments. She was the recipient of 20+ Intel Corporation awards for contributions to major product and industry initiatives.

Professional Affiliations:

• Member of American Society for Engineering Education (ASEE)
• Member of Society of Women Engineers (SWE)

Research Interest and Expertise:

• Computer Architecture
• Platform Interconnect
• Power/Performance Architecture
• Machine Learning
• Quantum Computing

Courses Taught:

• ECE 4/525 Digital Integrated Circuit Design I
• ECE 4/585 Microprocessor System Design
• ECE 4/586 Computer Architecture
• ECE 5/687 Advanced Computer Architecture I
• ECE 5/688 Advanced Computer Architecture II