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Hybrid CMOS/Nanogrid Architectures and Circuits
Monday, November 2, 2009 - 12:00pm to Wednesday, November 4, 2009 - 1:50pm

“Hybrid CMOS/Nanogrid Architectures and Circuits”
November 2 & November 4
12:00‐1:50 p.m.
FAB 150

Dr. Dan Hammerstrom, Associate Dean of Research for MCECS, will be presenting two, 2‐hour tutorials titled, “Hybrid CMOS/ Nanogrid Architectures and Circuits.” The goal of this 4‐hour tutorial is to review the recent work on the development of hybrid digital semiconductor/nano‐electronic integrated circuits. The nano‐electroniccircuits described here are primarily nanogrid (nano‐crossbar) structures. These structures will most likely be fabricated on top of traditional CMOS technology, often in a hybrid architecture called CMOL. It is likely that such nanogrid technologies will be the first nanoelectronic technologies to be manufactured in volume and find wide‐spread use. The basics of nanogrid techniques as well as some sample architectures and simulations will be presented, including terabit‐scale memories, FPGA‐like reconfigurable circuits.

In addition, the state of the art in nanogrid fabrication will be discussed, such as the recent experimental demonstration of reproducible crosspoint devices and nanowire crossbars with 15‐nm‐scale half‐pitch. Much of this tutorial has been borrowed from “Hybrid CMOS/Nanoelectronic Circuits: Opportunities and Challenges,” a tutorial offered by K. Likharev, D. Strukov, and G. Rose at ISCAS 2008, with the authors’ permission.

Dr. Hammerstrom received his Ph.D. at University of Illinois at Urbana‐Champaign. He has previously held positions at Cornell University, OGI and Intel. He founded Adaptive Solutions, Inc., which specialized in high performance silicon technology (the CNAPS chip set) for image processing and pattern recognition. He currently holds joint appointments at OHSU and Halmstad University, Halmstad, Sweden.