Search Google Appliance


Electrical and Computer Engineering Seminar: Small Signal Cache Array Design Methodology and Performance Verification
Friday, May 19, 2006 - 2:00pm to Friday, May 19, 2006 - 3:00pm

The Department of Electrical and Computer Engineering (ECE) at PSU's Maseeh College of Engineering and Computer Science presents as part of the ECE507 Seminar Spring 2006 Series: Small Signal Cache Array Design Methodology and Performance Verification.

Title: "Small Signal Cache Array Design Methodology and Performance Verification"

Speaker: Dr. Issam Abu-Khater, Solution and Support Department, Intel Corporation

Date: May 19, 2006

Time: 2:00 - 3:00 p.m.

Location: 102EB, Fariborz Maseeh Auditorium, New Engineering Building, 1930 SW Fourth Avenue, Portland, Oregon 97201 (E-10 on map)

This series is free and open to the public. For further information, contact the Department of Electrical and Computer Engineering, (503) 725-3806 or

For more information on upcoming seminars, please visit the Department Web site:

Cache design and performance verification (PV) is an important aspect of current and future microprocessor design. Caches occupy a large area of the chip, consist of a huge number of transistor count, and exhibit higher layout density compared to other circuitry. Cache performance is also crucial to the performance of microprocessors. With the increase in the size of on chip caches and the use of small signal sensing, the design and verification of caches requires a methodology that covers all aspects of the design including identifying analog parts, performing dynamic simulation for verification of analog circuitry, and studying/fixing races, performing PV on all EBB including timing, noise, ERC and RV. The presentation will explore various aspects of cache design methodology.

Speaker Biography
Dr. Issam Abu-Khater is a 1995 Ph.D. graduate from the University of Waterloo, Ontario, Canada. His thesis dealt with Low Power Low Voltage CMOS/BiCMOS Digital Circuit Design. Dr. Abu-Khater joined Intel Corporation in 1995 and worked on cache design, dynamic design methodologies, and earned the title of Technical Lead in the area of "Post Layout Dynamic Circuit Simulation Methodology, Extraction, and RC manipulation." Recently Dr. Abu-Khater joined the Intel Solution and Support Department and is responsible for supporting FUB design flows, methodology, and tools across microprocessor design. Issam is co-author of the book Advanced Low-power Digital Circuit Techniques and holds a USA patent on implementation of conditional sum adder.