Dan Hammerstrom

Dan Hammerstrom

Professor Emeritus

Contact:
Fourth Avenue Building 20-18
(503) 725-3820
dwh@pdx.edu

Education:
Ph.D. University of Illinois - Urbana/Champaign
M.S.E.E. Stanford University
B.S.E.E. Montana State University (with Distinction) 

Research Interests:

  • Biologically Inspired Computing, algorithms and implementation
  • Biologically Inspired Machine Learning

Profile:
From 1977 to 1980, Dr. Hammerstrom was an Assistant Professor in the Electrical Engineering Department at Cornell University. In 1980 he joined Intel in Oregon, where he was involved in computer architecture and VLSI design. In 1988 he founded Adaptive Solutions, Inc., which specialized in high performance silicon technology (the CNAPS chip set) for image processing, neural network emulation, and pattern recognition.  In 1998 he joined the Oregon Graduate Institute, and then moved to Portland State in 2005. 

Dr. Hammerstrom was a Program Manager at DARPA from March 2012 to March 2016.  He has been a Visiting Scientist at the Royal Institute of Technology in Stockholm, Sweden and the NASA Ames Research Center. He currently has a joint faculty appointment with Halmstad University, Halmstad Sweden.


Professional Affiliations: 

  • IEEE Life Fellow   

Awards and Recognition:

March 2016 Dr. Hammerstrom was awarded the Office of the Secretary of Defense Medal for Exceptional Public Service.

Selected Publications:  

1. D. Nkonov, G. Csaba, W. Porod, T. Shibata, D. Voils, D., Hammerstrom, I. Young, and G. Bourianoff, "Coupled-Oscillator Associative Memory Array Operation for Pattern Recognition," IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol. 1, pp. 85-93, 2015

2. M.S. Zaveri, D. Hammerstrom, "Performance/price estimates for cortex-scale hardware: A design space exploration," Neural Networks, (Archival Journal of the International Neural Network Society), Elsevier, April, 2011, Pages: 291-304, DOI:10.1016/j.neunet.2010.12.003.

3. Mazad S. Zaveri and Dan Hammerstrom, “Nano/CMOS implementations of Inference in Bayesian Memory – An Architecture Assessment Methodology,” IEEE Transactions on Nanotechnology, Vol. 9, No. 2, March 2010, pp. 194-211.

4. A. Mathuria, D.W. Hammerstrom, "Approximate Pattern Matching using Hierarchical Graph Construction and Sparse Distributed Representation," International Conference on Neuromorphic Systems, Knoxville, TN, July 23-5, 2019

5. Kamela C. Rahman, Dan Hammerstrom, Yiwei Li, Hongyan Castagnaro, and Marek A. Perkowski, “Methodology and Design of a Massively Parallel Memristive Stateful IMPLY Logic based Reconfigurable Architecture”,  IEEE Transactions on Nano-technology, Volume: 15, Issue: 4, July 2016.