Dan Hammerstrom received a Ph.D. in electrical engineering from the University of Illinois at Urbana-Champaign. He was an Assistant Professor in the Electrical Engineering Department at Cornell University, and then joined Intel in Oregon where he participated in the development and implementation of the iAPX-432, the i960, and iWarp. He joined the faculty of the Computer Science and Engineering Department at the Oregon Graduate Institute in 1985 as an Associate Professor.
At OGI he developed the CNAPS architecture, which was an SIMD architecture that became an enabling technology for a number of pattern recognition and neural network algorithms. In addition, he founded a company, Adaptive Solutions, for the commercialization of CNAPS. By using laser fused processor redundancy, a CNAPS chip had 64 processors, each with 8KB of static RAM memory. Each CNAPS chip contained an unprecedented 11 million functional transistors, about 20x larger than most commercial chips in the early 1990s, with a performance of 3.2 billion digital, 8 and 16-bit, operations per second.
The architecture represented a balance of a number of different objectives. Although aimed primarily at implementing neural network and pattern recognition algorithms, it was specialized enough to provide 100-1000x performance improvement for these algorithms and yet flexible enough to allow a range of computation including feature extraction and traditional image processing. By handling a wider range of computations, the negative effects of Amdahl’s law were minimized and cost-performance enhanced.
After Adaptive Solutions, Dr. Hammerstrom returned to academia where he is now a Professor in the Electrical and Computer Engineering Department and Associate Dean for Research in the Maseeh College of Engineering and Computer Science at Portland State University. Dr. Hammerstrom holds joint appointments in the Biomedical Engineering Division of the Oregon Health & Science University, and in the IDE (Information, Computation, and Electronics) Department at Halmstad University, Halmstad, Sweden.
He has been an Associate Editor for the IEEE Transactions on Neural Networks, the Journal of the International Neural Network Society (INNS), and the International Journal of Neural Networks. He is currently an Associate Editor for the IEEE Transactions on Nanotechnology. He has authored over seventy research papers and eight book chapters, and holds seven patents. Dr. Hammerstrom has been a Visiting Scientist at the Royal Institute of Technology in Stockholm and the NASA Ames Research Center.