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Improving Next Generation Circuits with Nanotechnnology
Improving Next Generation Circuits with Nanotechnnology

 

Transistors amplify signals and control currents. They're the workhorses of microprossors and microprossors power our way of life in the 21st Centruy. The more transistors you can fit onto the silicon wafers that form the base of computer chips, the more processing power the chip will have. This is the conributing factor involved in a problem fast approaching the microprocessor industry. 

Each new generation of processor, if it is to really be an improvement over previous generations, necessitates the addition of greater and greater numbers of transistors. In 1958, Jack Kilby, the inventor of the integrated circuit, managed to cram one transistor into his design. Today’s modern integrated circuits contain over 2.6 billion individual electronic transistors in a 1 cm2 space.

The innovations that have made this giant leap possible are the driving force behind the unprecedented technological advances of the last sixty years. If we want to continue on this trajectory, however, and if Moore’s law continues to prove true, then the industry is going to need to find ways to integrate more and more transistors into a finite space.

Current state of the art tools can shrink transistor template to sizes of 50 nanometers2 (nm2). At smaller sizes errors are introduced that can lead to failure in electronic components. With work funded by Intel, Professor of chemistry, Dr. Shankar Rananavare believes he and his graduate students have found a way to bridge the gap between where the industry currently stands and even smaller transistor templates.

The way transistor templates are etched into silicon wafers now is through a process similar to photography. Photolithography is the industry standard. It’s the way chips are made. A silicon wafer is coated with chemicals which harden when exposed to UV light. In dark rooms, light is shown through a negative of the template and then through a miniaturizing lens and on to the coated wafer. When repeated a number of times, this photo etching leaves the transistor template. This process works great up to that 50 nm2 size.

Dr. Rananavare’s innovation is not out to reinvent the wheel. Why change an industry accepted standard? Rather, Dr. Rananavare’s method is to add a step in this process. By introducing discrete gold nanoparticles as guides in the photo etching process, Dr. Rananavare and his graduate students were able to show that irregularities in the transistor template could be overcome at a smaller scale.

“In the lab we study a range of nanomaterial. We study nanoparticles, nanowires, lithography, and I’m always on the lookout for bottlenecks in industries where nanotechnology can provide solutions to problems."

—Shankar Rananavare

“This was a problem a colleague, James Blackwell, at Intel brought to my attention. I thought it would be a great opportunity for my students to work on. The problem was, ‘how do we get smaller transistor templates than is currently possible—templates for 20 nm transistors or even smaller.”

According to Dr. Rananavare, there is another technology out there, that like his can solve this problem, but the disadvantage of that technology is that it is expensive, it’s not the industry standard, and it’s much slower than current practices. Dr. Rananavare’s method of applying gold nanoparticles as a physical template in conjunction with the ‘negative’ template used in the photo etching process works within the already existing top down structure used by major processor producers like Intel and Texas Instruments.

“I’ve found that a lot of the time it is integration that makes the difference that leads to innovation,” Dr. Rananavare said. “Solutions that do not require a major change to systems already accepted by industries. Innovations are fantastic when they’re cheap and easily implemented within existing technology and methods.”

The office of Innovation & Intellectual Property (IIP) has worked with Dr. Rananavare to evaluate the market potential of his application of gold nanoparticles to the fabrication of integrated circuit structures, hiring consulting firm TreMonti to perform a detailed analysis of the technology and investigate possible partnerships. IIP has also filed a provisional patent application and extended licensing options to Rananavare’s grant partner, Intel.

By innovating within the accepted practices and technologies, Dr. Rananavare has potentially solved one of the problems facing our modern electronics industries: the ability to fabricate silicon wafers capable of housing transistors of sizes smaller than 50 nm2

“What we try to do in our lab is put a new twist on what can be done with existing nanotechnology,” Dr. Rananavare said. “This technology can be adapted to all kinds of applications. But what we’re really interested in are the practical things: how nanotechnology can be put to use in practical ways. This is why I like working with companies like Intel and Monsanto. Circuit templates and herbicide delivery are nanoscale problems. Working on these problems ultimately helps improve the way we live. Making processors better. Reducing the chemicals in the environment. You have to work on the big and little problems; hit singles and homeruns. I believe that’s what my students and I are trying to do.”