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Electrical and Computer Engineering Seminar: Formal Verification
Friday, January 27, 2006 - 2:00pm to Friday, January 27, 2006 - 3:00pm

The Department of Electrical and Computer Engineering (ECE) at PSU's Maseeh College of Engineering and Computer Science presents as part of the ECE507 Seminar Winter 2006 Series: Formal Verification.

 
Title: "Formal Verification"

Speaker: Carl Pixley, Ph.D., Director of Formal Verification, Synopsys, Inc.

Date: January 27, 2006

Time: 2:00 - 3:00 p.m.

Location: 102EB, Fariborz Maseeh Auditorium, New Engineering Building, 1930 SW Fourth Avenue, Portland, Oregon 97201 (E-10 on map)

This series is free and open to the public. For further information, contact the Department of Electrical and Computer Engineering, (503) 725-3806 or info@ece.pdx.edu.

For more information on upcoming seminars, please visit the Department Web site: http://www.ece.pdx.edu/ece.507.graduate.seminar.schedule/current.htm

Abstract:

Formal equivalence is a well-established topic in EDA. I will quickly review Boolean equivalence and talk about some difficult problems. Then I will discuss sequential equivalence and cite several different approaches to its definition and solution. Finally, a discussion of transaction-level to RT level equivalence will be discussed focusing on our new Hector technology and some competitors. The main point is that equivalence verification is necessary for enabling various approaches to synthesis and other EDA tools. For example, Hector is necessary to enable ESL design.