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Electrical and Computer Engineering Seminar: Defect Screening Using Statistical Modeling of IDDQ Test Response Data
Friday, May 26, 2006 - 2:00pm to Friday, May 26, 2006 - 3:00pm

The Department of Electrical and Computer Engineering (ECE) at PSU's Maseeh College of Engineering and Computer Science presents as part of the ECE507 Seminar spring 2006 Series: Circuit Reliability Challenges.

Title: "Defect Screening Using Statistical Modeling of IDDQ Test Response Data."

Speaker: Ritesh Turakhia, ECE Ph.D. student, PSU

Date: May 26, 2006

Time: 2:00 - 3:00 p.m.

Location: 102EB, Fariborz Maseeh Auditorium, New Engineering Building, 1930 SW Fourth Avenue, Portland, Oregon 97201 (E-10 on map)

This series is free and open to the public. For further information, contact the Department of Electrical and Computer Engineering, (503) 725-3806 or info@ece.pdx.edu.

For more information on upcoming seminars, please visit the Department Web site: http://www.ece.pdx.edu/ece.507.graduate.seminar.schedule/current.htm

Abstract:

In nanometer CMOS processes, it has become increasingly difficult to identify the fails by applying logic test patterns to the device on an Automatic Test Equipment (ATE). Simple on-tester go/no-go tests fail to capture latent defects that directly impact the reliability of the product being tested and add to the overall product cost. Increasing implementation challenges and reducing efficacies of the burn-in, I DDQ and voltage stress tests are the main reasons that the 2005 International Technology Roadmap for Semiconductors (ITRS) lists "screening for reliability" as the second most difficult challenge for the IC industry. Formulating new reliability screens based on statistical modeling of test data is part of the active research conducted at the Integrated Circuit Design & Test Laboratory (ICDT) at Portland State University.

In this lecture Ritesh Turakhia will present the foundation of Statistical Post-Processing (SPP)-based methods that are joint developments between the PSU ICDT and LSI Logic. Using the raw data generated from ATE and wafer sort maps, off-tester SPP modules analyze test response statistics to identify statistical outliers and downgrade these otherwise passing dies. My talk is going to focus on post-processing modules that include advanced statistical IDDQ tests and Nearest Neighbor Residual (NNR). An IDDQ SPP outlier screen will be presented which is based on the computation of statistically independent sources of variation in the IDDQ measurements. Outliers are separated from the sample population based on residuals computed using these sources and a nearest neighbor spatial signature. When viewed from this new perspective the transformed IDDQ test response increases the ability to identify the dies with outlier behavior. An algorithm is presented for applying the proposed technique in production. The screen is demonstrated with 180nm and 110nm volume data and shown to effectively identify the outliers at the 110nm technology node. This data-driven framework provides multiple statistical views of the data to isolate outliers without increases in test time or test cost.

Speaker Biography

Ritesh Turakhia is a Ph.D. student at Portland State University working with Dr. Robert Daasch in the Integrated Circuit Design and Test Laboratory. His research interests include developing defect-based tests and statistical test analysis for defect identification and screening. Ritesh has an MS in electrical engineering from Colorado State University and is an activte student member of the IEEE.