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Bayesian Memory based Cortical Models onto CMOS and CMOL: Hardware Architectures and performance/price
Friday, November 21, 2008 - 2:00pm to Friday, November 21, 2008 - 3:00pm

SPEAKER:
Mazad Zaveri

PSU Ph.D. Candidate

WHERE:
Cramer Hall, Room 171: 1721 SW Broadway

ABSTRACT:
We present a Bayesian memory Module (BM), which is a highly simplified and generic model of the neocortex. This BM is derived from the George and Hawkins' cortical model by extracting the generic operating mechanisms from the algorithm. We then investigate the viable mappings of this generic BM onto CMOS and (hybrid-nanotechnology) CMOL, and propose various baseline architectures for the same. Several architectural configurations are analyzed, including traditional circuits and nano-scale circuits, and digital and mixed-signal designs. The baseline performance/price is then estimated based on system-level architectures, worst case design considerations, and hardware virtualization assumptions. The results clearly suggests that CMOS technology is not a candidate for building scalable cognitive systems. Whereas, CMOL emerges as an excellent canditate towards building scalable cognitive nanoarchitectures, especially because these are approaching biological densities. In summary, we present a generalized methodology of architecting, analyzing and investigating cognitive hardware architectures.

BIO:
Mazad S. Zaveri received B.E. degree in Instrumentation and Control Engineering from Nirma Institute of Technology/Gujarat University in 2000; M.S.E. degree in Electrical Engineering, specializing in Electronic and mixed-signal circuit design from Arizona State University. During 2003-2004 he was a research assistant at Oregon Graduate Institute/OHSU working with Professor Dan Hammerstrom on biologically-inspired Enhanced Vision System (EVS) for aircraft landing guidance, in collaboration with Max-Viz Inc. Since 2005, he is a Ph.D. candidate in the Department of Electrical and Computer Engineering, Portland State University, working with Professor Dan Hammerstrom. His research interests include architecting and investigating hardware-architectures for neural networks, associative memories, and biologically-inspired cognitive algorithms, using CMOS and nanotechnology based digital and mixed-signal circuits.