When: Friday, April 19th from 2:00pm -3:00pm
Where: Engineering Building, 1930 SW 4th Ave, Room EB 102
Abstract: Errors and malfunctions in computing systems can cost millions of dollars to our economy, lead to loss of human life, and severely subvert our national security. Verification and validation techniques aim to reduce this cost by ensuring that behavior of computing systems correspond to designer intentions and user expectations. However, state-of-the-art verification and validation techniques themselves are expensive, complex to use, and do not scale to the scale and complexity of modern, large- scale computing systems.
In this talk, I will discuss challenges in verification and validation of large-scale computing systems, focusing in particular on post-silicon functional validation and debug. Post-silicon validation is currently the dominant contributor to validation cost and directly affects quality and time-to-market of a new computing system or platform. Challenges in post-silicon validation arise from high complexity of the design as well as limited observability and controllability of the internal states of the design during normal execution. I will present recent research contributions on ameliorating observability limitations through formal analysis of pre-silicon designs. Our contributions include (1) verified state restoration approaches from a limited set of observable signals, and (2) design of integrity units to provide provable post-silicon guarantees.
Our work has found application in industrial tool flows. I will draw from this experience to identify some key challenges in the verification and validation techniques for current and future systems, and point to possible approaches to overcoming them through cooperation of design and verification.
Bio: Sandip Ray is a Research Scientist at Strategic CAD Labs, Intel Corporation. His current research focus is on developing post-silicon validation infrastructure for next-generation microprocessor and SoC designs. In particular, he leads multi-team projects on observability constraints and metrics for post-silicon debug quality, and techniques for post-silicon test readiness. Before joining Intel, Ray worked as a Research Scientist at University of Texas at Austin, where he developed formal verification techniques for mathematical analysis of diverse computing systems ranging from synthesized hardware designs to Java programs. His academic work was supported by National Science Foundation, Defense Advanced Research Projects Agency, and Semiconductor Research Corporation. Ray is the author of one book, as well as more than 30 peer-reviewed research articles on system validation and verification techniques. He has served on the program committee of more than 15 international meetings and conferences, as co-chair for the International Conference on Formal Methods in Computer-Aided Design (FMCAD 2013) and International Workshop on the ACL2 Theorem Prover and Its Applications (ACL2 2009), as a guest editor for ACM Transactions on Design Automation of Electronic Systems and Journal of Electronic Testing Theory and Applications. His other interests include distributed systems, computer architecture, analysis of algorithms, and logic. Ray has a Ph.D in Computer Science from the University of Texas at Austin and is a member of IEEE and ACM.